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author | Matt Ettus <matt@ettus.com> | 2010-04-15 21:27:03 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-04-15 21:27:03 -0700 |
commit | 23316f1ac73c917757a70980c3a9f251852ee426 (patch) | |
tree | c2b296176ae18648f7d201f345a95b327dbc3feb /usrp2/top/u1e/u1e.v | |
parent | d94a0fbea165463a132006a15eb8548cde79a4d2 (diff) | |
download | uhd-23316f1ac73c917757a70980c3a9f251852ee426.tar.gz uhd-23316f1ac73c917757a70980c3a9f251852ee426.tar.bz2 uhd-23316f1ac73c917757a70980c3a9f251852ee426.zip |
added pps and time capability
Diffstat (limited to 'usrp2/top/u1e/u1e.v')
-rw-r--r-- | usrp2/top/u1e/u1e.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index ab270879c..b8f716d26 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -20,7 +20,8 @@ module u1e input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls - inout [15:0] io_tx, inout [15:0] io_rx + inout [15:0] io_tx, inout [15:0] io_rx, + input PPS_IN ); // FPGA-specific pins connections @@ -50,6 +51,7 @@ module u1e .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), - .io_tx(io_tx), .io_rx(io_rx) ); + .io_tx(io_tx), .io_rx(io_rx), + .pps_in(PPS_IN) ); endmodule // u1e |