diff options
| author | Matt Ettus <matt@ettus.com> | 2010-03-26 11:30:13 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-03-26 11:30:13 -0700 |
| commit | 7a3064b67172aea1be00d188bdd79185a7df2ecf (patch) | |
| tree | 3be087c9d1a37a855fa54097d751b92053c16af5 /usrp2/top/u1e/u1e.ucf | |
| parent | f979a9d4e7b9664e046aaca54357e46782c4aa51 (diff) | |
| download | uhd-7a3064b67172aea1be00d188bdd79185a7df2ecf.tar.gz uhd-7a3064b67172aea1be00d188bdd79185a7df2ecf.tar.bz2 uhd-7a3064b67172aea1be00d188bdd79185a7df2ecf.zip | |
connect 2 clock gen controls and 3 status pins to the wishbone so they can be read/controlled from SW
Diffstat (limited to 'usrp2/top/u1e/u1e.ucf')
| -rw-r--r-- | usrp2/top/u1e/u1e.ucf | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 27f507c6b..c39759d0b 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -105,11 +105,11 @@ NET "cgen_sclk" LOC = "R5" ; NET "cgen_sen_b" LOC = "T1" ; ## Clock gen control -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; +NET "cgen_st_status" LOC = "D4" ; +NET "cgen_st_ld" LOC = "D1" ; +NET "cgen_st_refmon" LOC = "E1" ; +NET "cgen_sync_b" LOC = "M1" ; +NET "cgen_ref_sel" LOC = "J1" ; ## Debug pins NET "debug_led<2>" LOC = "T5" ; |