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| author | Matt Ettus <matt@ettus.com> | 2010-02-16 22:49:02 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-02-16 22:49:02 -0800 |
| commit | d4649caee02a1c76802dc4f8d7d76bb31b14ce09 (patch) | |
| tree | d64c7c7b0496690ac01f865de9b4a7db32c3b7eb /usrp2/top/u1e/tb_u1e.v | |
| parent | b115e4d7661d64c6d20f0421908622b56a91e950 (diff) | |
| download | uhd-d4649caee02a1c76802dc4f8d7d76bb31b14ce09.tar.gz uhd-d4649caee02a1c76802dc4f8d7d76bb31b14ce09.tar.bz2 uhd-d4649caee02a1c76802dc4f8d7d76bb31b14ce09.zip | |
wishbone bridge now with minimal functionality. Need to check
timing and handle wait states.
Diffstat (limited to 'usrp2/top/u1e/tb_u1e.v')
| -rw-r--r-- | usrp2/top/u1e/tb_u1e.v | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 6e0c60e17..85d2b49f0 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -6,8 +6,12 @@ module tb_u1e(); wire [2:0] debug_led; wire [31:0] debug; wire [1:0] debug_clk; - - + + initial begin + $dumpfile("tb_u1e.lxt"); + $dumpvars(0,tb_u1e); + end + // GPMC wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; wire [15:0] EM_D; @@ -15,11 +19,16 @@ module tb_u1e(); wire [1:0] EM_NBE; reg clk_fpga = 0; - always #100 clk_fpga = ~clk_fpga; + always #15.625 clk_fpga = ~clk_fpga; u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + + gpmc_model gpmc_model + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); -endmodule // u1e +endmodule // tb_u1e |