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authorMatt Ettus <matt@ettus.com>2010-02-16 18:47:22 -0800
committerMatt Ettus <matt@ettus.com>2010-02-16 18:47:22 -0800
commitb115e4d7661d64c6d20f0421908622b56a91e950 (patch)
treeb684f1b1266640ab146bdb399c8e82ca3769a329 /usrp2/top/u1e/tb_u1e.v
parentc1ddc5c082c053eaa46c8bc87064d3e3e56b0d9e (diff)
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first cut at gpmc <-> wb bridge, split u1e into core, top, and tb
Diffstat (limited to 'usrp2/top/u1e/tb_u1e.v')
-rw-r--r--usrp2/top/u1e/tb_u1e.v25
1 files changed, 25 insertions, 0 deletions
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
new file mode 100644
index 000000000..6e0c60e17
--- /dev/null
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module tb_u1e();
+
+ wire [2:0] debug_led;
+ wire [31:0] debug;
+ wire [1:0] debug_clk;
+
+
+ // GPMC
+ wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
+ wire [15:0] EM_D;
+ wire [10:1] EM_A;
+ wire [1:0] EM_NBE;
+
+ reg clk_fpga = 0;
+ always #100 clk_fpga = ~clk_fpga;
+
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+endmodule // u1e