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| author | Matt Ettus <matt@ettus.com> | 2010-02-16 22:49:02 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-02-16 22:49:02 -0800 |
| commit | d4649caee02a1c76802dc4f8d7d76bb31b14ce09 (patch) | |
| tree | d64c7c7b0496690ac01f865de9b4a7db32c3b7eb /usrp2/top/u1e/cmdfile | |
| parent | b115e4d7661d64c6d20f0421908622b56a91e950 (diff) | |
| download | uhd-d4649caee02a1c76802dc4f8d7d76bb31b14ce09.tar.gz uhd-d4649caee02a1c76802dc4f8d7d76bb31b14ce09.tar.bz2 uhd-d4649caee02a1c76802dc4f8d7d76bb31b14ce09.zip | |
wishbone bridge now with minimal functionality. Need to check
timing and handle wait states.
Diffstat (limited to 'usrp2/top/u1e/cmdfile')
| -rw-r--r-- | usrp2/top/u1e/cmdfile | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..5e4db5c65 --- /dev/null +++ b/usrp2/top/u1e/cmdfile @@ -0,0 +1,19 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models + +# Open Cores +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog + |