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| author | Matt Ettus <matt@ettus.com> | 2010-02-18 18:03:26 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-02-18 18:03:26 -0800 |
| commit | e56b4767451dcdca41512faba634b812e44d2e1d (patch) | |
| tree | e1db75cafea6fa739ded87024cf74bd726c7ac60 /usrp2/top/u1e/cmdfile | |
| parent | 1912ff60acd490a24204a7596e373e9aef9276cd (diff) | |
| download | uhd-e56b4767451dcdca41512faba634b812e44d2e1d.tar.gz uhd-e56b4767451dcdca41512faba634b812e44d2e1d.tar.bz2 uhd-e56b4767451dcdca41512faba634b812e44d2e1d.zip | |
Fixed paths to help icarus find opencores and xilinx models. Added Xilinx global set and reset module.
Diffstat (limited to 'usrp2/top/u1e/cmdfile')
| -rw-r--r-- | usrp2/top/u1e/cmdfile | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile index 5e4db5c65..291c723b8 100644 --- a/usrp2/top/u1e/cmdfile +++ b/usrp2/top/u1e/cmdfile @@ -10,10 +10,11 @@ # Models -y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims # Open Cores --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog |