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| author | Matt Ettus <matt@ettus.com> | 2010-03-26 17:12:07 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-03-26 17:12:07 -0700 |
| commit | b9e715983eaa625f65f1ac4d18c7fbc9e5ace4cd (patch) | |
| tree | 6ad97edce41f0a4bbc77179126c0077305d40d6a /usrp2/top/u1e/Makefile | |
| parent | 806a2de4cdd9794f6fba915e32534fd2a0f31cb5 (diff) | |
| download | uhd-b9e715983eaa625f65f1ac4d18c7fbc9e5ace4cd.tar.gz uhd-b9e715983eaa625f65f1ac4d18c7fbc9e5ace4cd.tar.bz2 uhd-b9e715983eaa625f65f1ac4d18c7fbc9e5ace4cd.zip | |
connect up the 16 bit spi core
Diffstat (limited to 'usrp2/top/u1e/Makefile')
| -rw-r--r-- | usrp2/top/u1e/Makefile | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 3412e227d..2b78b21bd 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -137,8 +137,7 @@ opencores/simple_pic/rtl/simple_pic.v \ opencores/spi/rtl/verilog/spi_clgen.v \ opencores/spi/rtl/verilog/spi_defines.v \ opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ +opencores/spi/rtl/verilog/spi_top16.v \ sdr_lib/acc.v \ sdr_lib/add2.v \ sdr_lib/add2_and_round.v \ |