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| author | Matt Ettus <matt@ettus.com> | 2010-04-01 17:05:50 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-04-01 17:05:50 -0700 |
| commit | 52c8d239ac4b2c448a15b7cc2e2cadf6f296c3e0 (patch) | |
| tree | 42cf33184b93430a31b2fa410f267ed07e3ef10c /usrp2/top/u1e/Makefile | |
| parent | cce4104964c1e1930f85dbb0bb8b8f33086bd75e (diff) | |
| download | uhd-52c8d239ac4b2c448a15b7cc2e2cadf6f296c3e0.tar.gz uhd-52c8d239ac4b2c448a15b7cc2e2cadf6f296c3e0.tar.bz2 uhd-52c8d239ac4b2c448a15b7cc2e2cadf6f296c3e0.zip | |
added 16-bit wide atr controller
settings_bus_16 now handles variable address window sizes
split ctrl of nsgpio into ctrl (selector) and debug bits
Diffstat (limited to 'usrp2/top/u1e/Makefile')
| -rw-r--r-- | usrp2/top/u1e/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 2b78b21bd..a0f921485 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -54,7 +54,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ export SOURCE_ROOT := ../../../ export SOURCES := \ control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ +control_lib/atr_controller16.v \ control_lib/bin2gray.v \ control_lib/dcache.v \ control_lib/decoder_3_8.v \ |