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authorMatt Ettus <matt@ettus.com>2010-05-04 12:30:56 -0700
committerMatt Ettus <matt@ettus.com>2010-05-04 12:30:56 -0700
commit031becd1f05f0fbcab6a4f2be353292cd667a88f (patch)
tree33fd5a9c2580615e98baa6729671f07bdecac4e8 /usrp2/top/tcl
parentb30cbe85e8537de6a94e481a57033b5e57a73e12 (diff)
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add timing constraints. Just have main clock signal at 64 MHz for now.
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