fpga: print timing report after generate bin file

1 files changed, 30 insertions, 0 deletions

diff --git a/usrp2/top/python/check_timing.py b/usrp2/top/python/check_timing.py
new file mode 100755
index 000000000..c57e889d0
--- /dev/null
+++ b/usrp2/top/python/check_timing.py
@@ -0,0 +1,30 @@
+#!/usr/bin/env python
+#
+# Copyright 2011 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+import sys
+import re
+
+def print_timing_constraint_summary(twr_file):
+    output = ""
+    keep = False
+    for line in open(twr_file).readlines():
+        if 'Derived Constraint Report' in line: keep = True
+        if keep: output += line
+        if 'constraint' in line and 'met' in line: break
+    print("\n\n"+output)
+
+if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:])