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| author | Josh Blum <josh@joshknows.com> | 2012-03-09 16:53:11 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-16 11:29:18 -0700 |
| commit | fdf98d12a58548a929ce44a860d8981c707f3ec7 (patch) | |
| tree | 09bcfb1a67f14f9fcaba4642380f07f1c2c702ae /usrp2/top/USRP2 | |
| parent | f031d37713d47c5478e65587f7c095bd62ed9870 (diff) | |
| download | uhd-fdf98d12a58548a929ce44a860d8981c707f3ec7.tar.gz uhd-fdf98d12a58548a929ce44a860d8981c707f3ec7.tar.bz2 uhd-fdf98d12a58548a929ce44a860d8981c707f3ec7.zip | |
fifo ctrl: minor fixes for spi core, swap time define
Diffstat (limited to 'usrp2/top/USRP2')
| -rw-r--r-- | usrp2/top/USRP2/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/USRP2/Makefile b/usrp2/top/USRP2/Makefile index 10610c7dc..94480a811 100644 --- a/usrp2/top/USRP2/Makefile +++ b/usrp2/top/USRP2/Makefile @@ -70,7 +70,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" +"Verilog Macros" "FIFO_CTRL_NO_TIME=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |