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authorMatt Ettus <matt@ettus.com>2011-04-18 14:13:50 -0700
committerMatt Ettus <matt@ettus.com>2011-06-08 10:52:51 -0700
commit90c74cd45885ab2aba3d090a8deebd11b96c6d7c (patch)
treecc2bad819627c06804074bee359f9b8050b6dc94 /usrp2/top/USRP2
parent7b127e2f51f636baf1d39f46cc9afd09579bf74f (diff)
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u2/u2p: use new rx_frontend in u2 and u2p
Diffstat (limited to 'usrp2/top/USRP2')
-rw-r--r--usrp2/top/USRP2/u2_core.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 151ac27ae..0821277cc 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -283,7 +283,7 @@ module u2_core
.sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
.sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
- //////////////////////////////////////////////////////////////////////////////////////////
+ // ////////////////////////////////////////////////////////////////////////////////////////
// Reset Controller
system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
.ram_loader_rst_o(ram_loader_rst),
@@ -586,7 +586,7 @@ module u2_core
// ADC Frontend
wire [17:0] adc_i, adc_q;
- rx_frontend #(.BASE()) rx_frontend
+ rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a),