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| author | Nick Foster <nick@nerdnetworks.org> | 2011-06-10 15:03:19 -0700 |
|---|---|---|
| committer | Nick Foster <nick@nerdnetworks.org> | 2011-06-10 15:03:19 -0700 |
| commit | c0fadece89314f3a00892122c28caf187ce1a717 (patch) | |
| tree | 65683bc6a5b348e5f10c6da6a203cc86696ae05f /usrp2/top/N2x0/Makefile.N210R4 | |
| parent | 23c373f4ebea614a59f2032293b0264d93468fef (diff) | |
| download | uhd-c0fadece89314f3a00892122c28caf187ce1a717.tar.gz uhd-c0fadece89314f3a00892122c28caf187ce1a717.tar.bz2 uhd-c0fadece89314f3a00892122c28caf187ce1a717.zip | |
N2XX: this method for defining R3/R4 actually works
Diffstat (limited to 'usrp2/top/N2x0/Makefile.N210R4')
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N210R4 | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/N2x0/Makefile.N210R4 b/usrp2/top/N2x0/Makefile.N210R4 index 73747e544..01a9e19fd 100644 --- a/usrp2/top/N2x0/Makefile.N210R4 +++ b/usrp2/top/N2x0/Makefile.N210R4 @@ -45,7 +45,6 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -rev4_defs.v \ capture_ddrlvds.v \ u2plus_core.v \ u2plus.v \ @@ -67,7 +66,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "LVDS=1" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |