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| author | Josh Blum <josh@joshknows.com> | 2012-02-02 20:08:47 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-02 20:08:47 -0800 |
| commit | e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8 (patch) | |
| tree | 171f25a9e1da428de11e9b084da982ae07a7c5c9 /usrp2/top/N2x0/Makefile.N210R3 | |
| parent | 1ce83a07e188844d81db62d9e3027267fae97fb7 (diff) | |
| download | uhd-e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8.tar.gz uhd-e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8.tar.bz2 uhd-e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8.zip | |
dsp rework: rehash of the custom module stuff and readme
Diffstat (limited to 'usrp2/top/N2x0/Makefile.N210R3')
| -rw-r--r-- | usrp2/top/N2x0/Makefile.N210R3 | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/usrp2/top/N2x0/Makefile.N210R3 b/usrp2/top/N2x0/Makefile.N210R3 index 2514600f4..0b53ac951 100644 --- a/usrp2/top/N2x0/Makefile.N210R3 +++ b/usrp2/top/N2x0/Makefile.N210R3 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -8,6 +8,10 @@ TOP_MODULE = u2plus BUILD_DIR = $(abspath build$(ISE)-N210R3) +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + ################################################## # Include other makefiles ################################################## @@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extramfifo/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## @@ -67,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |