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author | Josh Blum <josh@joshknows.com> | 2012-02-02 20:08:47 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2012-02-02 20:08:47 -0800 |
commit | e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8 (patch) | |
tree | 171f25a9e1da428de11e9b084da982ae07a7c5c9 /usrp2/top/N2x0/Makefile.N200R4 | |
parent | 1ce83a07e188844d81db62d9e3027267fae97fb7 (diff) | |
download | uhd-e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8.tar.gz uhd-e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8.tar.bz2 uhd-e64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8.zip |
dsp rework: rehash of the custom module stuff and readme
Diffstat (limited to 'usrp2/top/N2x0/Makefile.N200R4')
-rw-r--r-- | usrp2/top/N2x0/Makefile.N200R4 | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/usrp2/top/N2x0/Makefile.N200R4 b/usrp2/top/N2x0/Makefile.N200R4 index 551f7a232..5c9ffd7a6 100644 --- a/usrp2/top/N2x0/Makefile.N200R4 +++ b/usrp2/top/N2x0/Makefile.N200R4 @@ -1,5 +1,5 @@ # -# Copyright 2008 Ettus Research LLC +# Copyright 2008-2012 Ettus Research LLC # ################################################## @@ -8,6 +8,10 @@ TOP_MODULE = u2plus BUILD_DIR = $(abspath build$(ISE)-N200R4) +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + ################################################## # Include other makefiles ################################################## @@ -24,7 +28,6 @@ include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs include ../../extramfifo/Makefile.srcs -include ../../custom/Makefile.srcs ################################################## @@ -69,7 +72,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "LVDS=1" +"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |