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| author | Josh Blum <josh@joshknows.com> | 2013-03-18 18:33:11 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2013-03-18 18:33:11 -0700 |
| commit | 81447a405eab9cfe154ebcf1d809d95269ed349a (patch) | |
| tree | 7f4e06a5e79c0ac939e6f4a1e0eacb0913155fbf /usrp2/top/E1x0 | |
| parent | a370cb47bbec9a237dfd50b5247d621cd8ab5f4e (diff) | |
| download | uhd-81447a405eab9cfe154ebcf1d809d95269ed349a.tar.gz uhd-81447a405eab9cfe154ebcf1d809d95269ed349a.tar.bz2 uhd-81447a405eab9cfe154ebcf1d809d95269ed349a.zip | |
e110: fixes from last commit
Diffstat (limited to 'usrp2/top/E1x0')
| -rw-r--r-- | usrp2/top/E1x0/Makefile.E110 | 1 | ||||
| -rw-r--r-- | usrp2/top/E1x0/timing.ucf | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110 index 329ab54ce..c2d3e39e6 100644 --- a/usrp2/top/E1x0/Makefile.E110 +++ b/usrp2/top/E1x0/Makefile.E110 @@ -50,7 +50,6 @@ simulator "ISE Simulator (VHDL/Verilog)" \ TOP_SRCS = \ ../B100/u1plus_core.v \ E1x0.v \ -DCM_GPMC.v \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ diff --git a/usrp2/top/E1x0/timing.ucf b/usrp2/top/E1x0/timing.ucf index b0e449298..1483c2a05 100644 --- a/usrp2/top/E1x0/timing.ucf +++ b/usrp2/top/E1x0/timing.ucf @@ -14,7 +14,7 @@ INST "EM_NCS6" TNM = gpmc_net; INST "EM_NWE" TNM = gpmc_net; INST "EM_NOE" TNM = gpmc_net; -TIMEGRP "gpmc_net" OFFSET = IN 5 ns VALID 10 ns BEFORE "EM_CLK" FALLING; +TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 10 ns BEFORE "EM_CLK" FALLING; #TIMEGRP "gpmc_net_out" OFFSET = OUT 13 ns AFTER "EM_CLK" RISING; //2 clock cyc per read #constrain interrupt lines |