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| author | Matt Ettus <matt@ettus.com> | 2011-10-26 15:44:08 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-10-26 15:57:22 -0700 |
| commit | 195cbeb81a7f53e92bb66053cd33aa1fe5c98157 (patch) | |
| tree | 748ac6901c89ac05065f06ee77105a8d2724e4dd /usrp2/top/E1x0 | |
| parent | 35b4a76effc67696aeadaf870ce446e3530a9151 (diff) | |
| download | uhd-195cbeb81a7f53e92bb66053cd33aa1fe5c98157.tar.gz uhd-195cbeb81a7f53e92bb66053cd33aa1fe5c98157.tar.bz2 uhd-195cbeb81a7f53e92bb66053cd33aa1fe5c98157.zip | |
u1p/u1e: partially redone atr and gpio redo
Diffstat (limited to 'usrp2/top/E1x0')
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index 025df3065..d40056844 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -298,6 +298,7 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + assign s1_ack = 0; assign s6_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; @@ -377,14 +378,13 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // GPIOs -- Slave #4 - wire [31:0] atr_lines; wire [31:0] debug_gpio_0, debug_gpio_1; nsgpio16LE nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .atr(),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); //////////////////////////////////////////////////////////////////////////// @@ -435,15 +435,6 @@ module u1e_core .strobe(set_stb),.addr(set_addr),.data(set_data) ); // ///////////////////////////////////////////////////////////////////////// - // ATR Controller -- Slave #6 - - atr_controller16 atr_controller16 - (.clk_i(wb_clk), .rst_i(wb_rst), - .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), - .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(run_rx0 | run_rx1), .run_tx(run_tx), .ctrl_lines(atr_lines)); - - // ///////////////////////////////////////////////////////////////////////// // Readback mux 32 -- Slave #7 wire [31:0] reg_test32; |