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authorNick Foster <nick@nerdnetworks.org>2011-08-10 15:54:32 -0700
committerNick Foster <nick@nerdnetworks.org>2011-08-10 15:54:32 -0700
commitc63dfca822ea1123af354a210b8c65a8a424665b (patch)
treebaf8ad3945eb3ccc20d4a1bdb608cc5b3164d1eb /usrp2/top/E1x0
parent43087d47403bf93bf03b61b9c79472239c44808f (diff)
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B100/E100: fix ATR RX mode pins not connected
Diffstat (limited to 'usrp2/top/E1x0')
-rw-r--r--usrp2/top/E1x0/u1e_core.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index c4fc16444..6189a8d13 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -148,7 +148,7 @@ module u1e_core
// RX ADC Frontend, does IQ Balance, DC Offset, muxing
wire [23:0] adc_i, adc_q; // 24 bits is total overkill here, but it matches u2/u2p
- wire run_rx, run_rx0, run_rx1;
+ wire run_rx0, run_rx1;
rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
(.clk(wb_clk),.rst(wb_rst),
@@ -462,7 +462,7 @@ module u1e_core
(.clk_i(wb_clk), .rst_i(wb_rst),
.adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso),
.we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack),
- .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines));
+ .run_rx(run_rx0 | run_rx1), .run_tx(run_tx), .ctrl_lines(atr_lines));
// /////////////////////////////////////////////////////////////////////////
// Readback mux 32 -- Slave #7