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authorMatt Ettus <matt@ettus.com>2011-06-07 16:48:30 -0700
committerMatt Ettus <matt@ettus.com>2011-06-07 16:48:30 -0700
commite4be5c906e8c1f0901ff7206b4b965a0abc7d8d2 (patch)
tree7c7d2f9697d9d873e3d6917da6a87e31cabbbc93 /usrp2/top/E1x0/tb_u1e.v
parentf0a9f021120eae604321edb9a97a7a5d8716da47 (diff)
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lots of renaming and moving around of toplevel directories to reflect product names
Diffstat (limited to 'usrp2/top/E1x0/tb_u1e.v')
-rw-r--r--usrp2/top/E1x0/tb_u1e.v41
1 files changed, 41 insertions, 0 deletions
diff --git a/usrp2/top/E1x0/tb_u1e.v b/usrp2/top/E1x0/tb_u1e.v
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+++ b/usrp2/top/E1x0/tb_u1e.v
@@ -0,0 +1,41 @@
+`timescale 1ps / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module tb_u1e();
+
+ wire [2:0] debug_led;
+ wire [31:0] debug;
+ wire [1:0] debug_clk;
+
+ xlnx_glbl glbl (.GSR(),.GTS());
+
+ initial begin
+ $dumpfile("tb_u1e.lxt");
+ $dumpvars(0,tb_u1e);
+ end
+
+ // GPMC
+ wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
+ wire [15:0] EM_D;
+ wire [10:1] EM_A;
+ wire [1:0] EM_NBE;
+
+ reg clk_fpga = 0, rst_fpga = 1;
+ always #15625 clk_fpga = ~clk_fpga;
+
+ initial #200000
+ @(posedge clk_fpga)
+ rst_fpga <= 0;
+
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga),
+ .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+ .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+ gpmc_model_async gpmc_model_async
+ (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+ .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6),
+ .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+endmodule // tb_u1e