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| author | Matt Ettus <matt@ettus.com> | 2011-06-07 16:48:30 -0700 |
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| committer | Matt Ettus <matt@ettus.com> | 2011-06-07 16:48:30 -0700 |
| commit | e4be5c906e8c1f0901ff7206b4b965a0abc7d8d2 (patch) | |
| tree | 7c7d2f9697d9d873e3d6917da6a87e31cabbbc93 /usrp2/top/E1x0/cmdfile | |
| parent | f0a9f021120eae604321edb9a97a7a5d8716da47 (diff) | |
| download | uhd-e4be5c906e8c1f0901ff7206b4b965a0abc7d8d2.tar.gz uhd-e4be5c906e8c1f0901ff7206b4b965a0abc7d8d2.tar.bz2 uhd-e4be5c906e8c1f0901ff7206b4b965a0abc7d8d2.zip | |
lots of renaming and moving around of toplevel directories to reflect product names
Diffstat (limited to 'usrp2/top/E1x0/cmdfile')
| -rw-r--r-- | usrp2/top/E1x0/cmdfile | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/usrp2/top/E1x0/cmdfile b/usrp2/top/E1x0/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/usrp2/top/E1x0/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + |