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| author | Josh Blum <josh@joshknows.com> | 2013-03-14 17:49:57 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2013-03-14 17:49:57 -0700 |
| commit | a370cb47bbec9a237dfd50b5247d621cd8ab5f4e (patch) | |
| tree | 3bd27bfb1f263a221f055218cddda90c15553e02 /usrp2/top/E1x0/Makefile.E110 | |
| parent | 8d91709d43f8df717abc8e05967e63c60887cd87 (diff) | |
| download | uhd-a370cb47bbec9a237dfd50b5247d621cd8ab5f4e.tar.gz uhd-a370cb47bbec9a237dfd50b5247d621cd8ab5f4e.tar.bz2 uhd-a370cb47bbec9a237dfd50b5247d621cd8ab5f4e.zip | |
e100: switch to fixed length xfers
Diffstat (limited to 'usrp2/top/E1x0/Makefile.E110')
| -rw-r--r-- | usrp2/top/E1x0/Makefile.E110 | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/E1x0/Makefile.E110 b/usrp2/top/E1x0/Makefile.E110 index e5be8d2fa..329ab54ce 100644 --- a/usrp2/top/E1x0/Makefile.E110 +++ b/usrp2/top/E1x0/Makefile.E110 @@ -50,7 +50,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ TOP_SRCS = \ ../B100/u1plus_core.v \ E1x0.v \ -E1x0.ucf \ +DCM_GPMC.v \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ |