diff options
| author | Josh Blum <josh@joshknows.com> | 2012-07-17 12:28:29 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-07-17 12:28:29 -0700 |
| commit | 9ecbfeb8ee52b6a59b8757cb259b325cebd05199 (patch) | |
| tree | b883bd36309c2d5fe07f8bc02e710afe0f7fc4af /usrp2/top/E1x0/Makefile.E100 | |
| parent | 0ff64ba45e9d26359297242504d0c06e47a36a38 (diff) | |
| download | uhd-9ecbfeb8ee52b6a59b8757cb259b325cebd05199.tar.gz uhd-9ecbfeb8ee52b6a59b8757cb259b325cebd05199.tar.bz2 uhd-9ecbfeb8ee52b6a59b8757cb259b325cebd05199.zip | |
e100: renamed top level for E100/E110 to E1x0
Some minor tweaks to gpmc_to_fifo + timing
Diffstat (limited to 'usrp2/top/E1x0/Makefile.E100')
| -rw-r--r-- | usrp2/top/E1x0/Makefile.E100 | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/top/E1x0/Makefile.E100 b/usrp2/top/E1x0/Makefile.E100 index 2b0ae8367..92334d987 100644 --- a/usrp2/top/E1x0/Makefile.E100 +++ b/usrp2/top/E1x0/Makefile.E100 @@ -5,7 +5,7 @@ ################################################## # Project Setup ################################################## -TOP_MODULE = E100 +TOP_MODULE = E1x0 BUILD_DIR = $(abspath build$(ISE)-E100) # set me in a custom makefile @@ -49,8 +49,8 @@ simulator "ISE Simulator (VHDL/Verilog)" \ ################################################## TOP_SRCS = \ ../B100/u1plus_core.v \ -E100.v \ -E100.ucf \ +E1x0.v \ +E1x0.ucf \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ |