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authorJosh Blum <josh@joshknows.com>2012-04-24 20:02:02 -0700
committerJosh Blum <josh@joshknows.com>2012-04-24 20:02:02 -0700
commit8a00096f9897fc6bb62e8fb7a5ce2fe336f91a8c (patch)
tree4eb447bdeba673f145886d12ce052c3fc74bfcf4 /usrp2/top/B100
parent600258c2ab0ad6284e9f6287ac340c1692984be6 (diff)
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b100: implement packet-end/flush cycle timeout
Diffstat (limited to 'usrp2/top/B100')
-rw-r--r--usrp2/top/B100/u1plus_core.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index c1d6767d1..74151ce98 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -413,7 +413,7 @@ module u1plus_core
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd9, 16'd3}; //major, minor
+ localparam compat_num = {16'd9, 16'd4}; //major, minor
wire [31:0] reg_test32;