Merge branch 'slave_fifo_rebase' into dsp_rework

Conflicts:
	usrp2/top/B100/u1plus_core.v

3 files changed, 27 insertions, 20 deletions

diff --git a/usrp2/top/B100/B100.ucf b/usrp2/top/B100/B100.ucf
index 69fd49971..c86501e72 100644
--- a/usrp2/top/B100/B100.ucf
+++ b/usrp2/top/B100/B100.ucf
@@ -43,17 +43,18 @@ NET "GPIF_D<2>"  LOC = "N9"  ;
 NET "GPIF_D<1>"  LOC = "P9"  ;
 NET "GPIF_D<0>"  LOC = "P8"  ;
 
-NET "GPIF_CTL<3>"  LOC = "N5"  ;
+##NET "GPIF_CTL<3>"  LOC = "N5"  ;
+NET "GPIF_CTL<3>"  LOC = "P12"  ;
 NET "GPIF_CTL<2>"  LOC = "M11"  ;
 NET "GPIF_CTL<1>"  LOC = "M9"  ;
 NET "GPIF_CTL<0>"  LOC = "M7"  ;
 
-NET "GPIF_RDY<3>"  LOC = "N11"  ;
-NET "GPIF_RDY<2>"  LOC = "T10"  ;
-NET "GPIF_RDY<1>"  LOC = "T4"  ;
-NET "GPIF_RDY<0>"  LOC = "R5"  ;
+##NET "GPIF_RDY<3>"  LOC = "N11"  ;
+##NET "GPIF_RDY<2>"  LOC = "T10"  ;
+NET "GPIF_SLWR"  LOC = "T4"  ;
+NET "GPIF_SLRD"  LOC = "R5"  ;
 
-NET "GPIF_CS"  LOC = "P12"  ;
+##NET "GPIF_CS"  LOC = "P12"  ;
 NET "GPIF_SLOE"  LOC = "R11"  ;
 NET "GPIF_PKTEND"  LOC = "P10"  ;
 NET "GPIF_ADR<0>"  LOC = "T11"  ;
diff --git a/usrp2/top/B100/B100.v b/usrp2/top/B100/B100.v
index f2d75c54e..b5691d1c3 100644
--- a/usrp2/top/B100/B100.v
+++ b/usrp2/top/B100/B100.v
@@ -23,8 +23,8 @@ module B100
    output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
 
    // GPIF
-   inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY,
-   input [1:0] GPIF_ADR, output GPIF_CS, output GPIF_SLOE, output GPIF_PKTEND,
+   inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output GPIF_SLOE, 
+   output [1:0] GPIF_ADR, output GPIF_SLWR, output GPIF_SLRD, output GPIF_PKTEND,
    input IFCLK,
    
    inout SDA_FPGA, inout SCL_FPGA, // I2C
@@ -156,9 +156,10 @@ module B100
    u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset),
 		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .debug_txd(), .debug_rxd(1'b1),
-		     .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY),
-		     .gpif_misc({GPIF_CS,GPIF_SLOE,GPIF_PKTEND}),
-		     .gpif_clk(IFCLK),
+		     
+		     .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_pktend(GPIF_PKTEND),
+		     .gpif_sloe(GPIF_SLOE), .gpif_slwr(GPIF_SLWR), .gpif_slrd(GPIF_SLRD),
+		     .gpif_fifoadr(GPIF_ADR), .gpif_clk(IFCLK),
 
 		     .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
 		     .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso),
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index b9a7e55a2..1981123bc 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -23,8 +23,9 @@ module u1plus_core
    output debug_txd, input debug_rxd,
    
    // GPIF
-   inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy,
-   output [2:0] gpif_misc, input gpif_clk,
+   inout [15:0] gpif_d, input [3:0] gpif_ctl, output gpif_sloe,
+   output gpif_slwr, output gpif_slrd, output gpif_pktend, output [1:0] gpif_fifoadr,
+   input gpif_clk,
    
    inout db_sda, inout db_scl,
    output sclk, output [15:0] sen, output mosi, input miso,
@@ -36,8 +37,8 @@ module u1plus_core
    input pps_in
    );
 
-   localparam TXFIFOSIZE = 11;
-   localparam RXFIFOSIZE = 11;
+   localparam TXFIFOSIZE = 12;
+   localparam RXFIFOSIZE = 12;
 
    // 64 total regs in address space
    localparam SR_RX_CTRL0 = 0;       // 9 regs (+0 to +8)
@@ -115,16 +116,21 @@ module u1plus_core
    setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx
      (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(),.changed(clear_tx));
+      
+   wire 	 run_rx0, run_rx1;
 
-   gpif #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
-   gpif (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d),
-	 .gpif_ctl(gpif_ctl), .gpif_rdy(gpif_rdy), .gpif_misc(gpif_misc),
+   slave_fifo #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
+   slave_fifo (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d),
+	 .gpif_ctl(gpif_ctl), .sloe(gpif_sloe), .slwr(gpif_slwr), .slrd(gpif_slrd),
+     .pktend(gpif_pktend), .fifoadr(gpif_fifoadr),
 	 
 	 .wb_clk(wb_clk), .wb_rst(wb_rst),
 	 .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
 	 .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
 	 .wb_ack_i(m0_ack), .triggers(8'd0),
 	 
+	 .dsp_rx_run(run_rx0 | run_rx1),
+	 
 	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx),
 	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
@@ -132,14 +138,13 @@ module u1plus_core
 	 
 	 .tx_underrun(tx_underrun_gpif), .rx_overrun(rx_overrun_gpif),
 
-	 .frames_per_packet(frames_per_packet),
+	 .test_len(0), .test_rate(0), .test_ctrl(0),
 	 .debug0(debug0), .debug1(debug1));
 
    // /////////////////////////////////////////////////////////////////////////
    // RX ADC Frontend, does IQ Balance, DC Offset, muxing
 
    wire [23:0] 	 rx_fe_i, rx_fe_q;  // 24 bits is total overkill here, but it matches u2/u2p
-   wire 	 run_rx0, run_rx1;
    
    rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
      (.clk(wb_clk),.rst(wb_rst),