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| author | Matt Ettus <matt@ettus.com> | 2011-08-24 15:39:00 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-26 13:24:17 -0700 |
| commit | 672795f93f8166262d93c78fcb35939809348c95 (patch) | |
| tree | c6714274e2765e34f3351badefc3b4184eba2dba /usrp2/top/B100 | |
| parent | 62ff57e24585359c6c216e59d3b01688140c02d5 (diff) | |
| download | uhd-672795f93f8166262d93c78fcb35939809348c95.tar.gz uhd-672795f93f8166262d93c78fcb35939809348c95.tar.bz2 uhd-672795f93f8166262d93c78fcb35939809348c95.zip | |
b100: gpif_rst resynced to gpif_clk
Diffstat (limited to 'usrp2/top/B100')
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 6a80eba76..b40083201 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -89,7 +89,7 @@ module u1plus_core .in(set_data),.out(),.changed(global_reset)); reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); - reset_sync reset_sync_gp(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); + reset_sync reset_sync_gp(.clk(gpif_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); wire [15:0] test_len; // ///////////////////////////////////////////////////////////////////////////////////// |