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| author | Josh Blum <josh@joshknows.com> | 2012-02-01 18:02:10 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-01 18:02:10 -0800 |
| commit | 7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f (patch) | |
| tree | 31bf389f0a241d4309bb042450dad4be81f39b3c /usrp2/top/B100 | |
| parent | 6bbcb202183c5a0ab5351a0c052981408e4719cb (diff) | |
| download | uhd-7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f.tar.gz uhd-7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f.tar.bz2 uhd-7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f.zip | |
dsp rework: custom engine module for rx/tx vita chain
Diffstat (limited to 'usrp2/top/B100')
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index 1981123bc..4c3acaa27 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -169,9 +169,10 @@ module u1plus_core .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .debug() ); - vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain0 + vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(0)) vita_rx_chain0 (.clk(wb_clk),.reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .vita_time(vita_time), .overrun(rx_overrun_dsp0), .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0), @@ -193,9 +194,10 @@ module u1plus_core .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .debug() ); - vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0)) vita_rx_chain1 + vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(1)) vita_rx_chain1 (.clk(wb_clk),.reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .vita_time(vita_time), .overrun(rx_overrun_dsp1), .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1), @@ -218,13 +220,14 @@ module u1plus_core wire [31:0] sample_tx; wire strobe_tx; - vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(0/*no engine*/), .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), .DSP_NUMBER(0)) vita_tx_chain (.clk(wb_clk), .reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), |