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authorJosh Blum <josh@joshknows.com>2012-02-02 20:08:47 -0800
committerJosh Blum <josh@joshknows.com>2012-02-02 20:08:47 -0800
commite64b6e6cddc2f9a5374cf23dbb8cf066d2fecbf8 (patch)
tree171f25a9e1da428de11e9b084da982ae07a7c5c9 /usrp2/top/B100/Makefile.B100
parent1ce83a07e188844d81db62d9e3027267fae97fb7 (diff)
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dsp rework: rehash of the custom module stuff and readme
Diffstat (limited to 'usrp2/top/B100/Makefile.B100')
-rw-r--r--usrp2/top/B100/Makefile.B10015
1 files changed, 11 insertions, 4 deletions
diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100
index 442b0b579..3cdbb62c0 100644
--- a/usrp2/top/B100/Makefile.B100
+++ b/usrp2/top/B100/Makefile.B100
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -7,7 +7,14 @@
##################################################
TOP_MODULE := B100
BUILD_DIR := build-B100/
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
+##################################################
+# Include other makefiles
+##################################################
include ../Makefile.common
include ../../fifo/Makefile.srcs
@@ -21,7 +28,6 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../gpif/Makefile.srcs
-include ../../custom/Makefile.srcs
##################################################
# Project Properties
@@ -64,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_MOD_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"