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author | Matt Ettus <matt@ettus.com> | 2010-12-30 10:56:53 -0800 |
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committer | Matt Ettus <matt@ettus.com> | 2010-12-30 10:56:53 -0800 |
commit | cc1f46382cd51c11b1d8ae175f3c7f86ea3df8e6 (patch) | |
tree | 3762217c97518792e03e8af596607287b26bf490 /usrp2/timing | |
parent | 19dafcc4ce1b53651cb7e4d471810cc81aa38528 (diff) | |
download | uhd-cc1f46382cd51c11b1d8ae175f3c7f86ea3df8e6.tar.gz uhd-cc1f46382cd51c11b1d8ae175f3c7f86ea3df8e6.tar.bz2 uhd-cc1f46382cd51c11b1d8ae175f3c7f86ea3df8e6.zip |
processor can read back vita_time at last pps
Diffstat (limited to 'usrp2/timing')
-rw-r--r-- | usrp2/timing/time_64bit.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v index 33eb2b25a..8122cc6ea 100644 --- a/usrp2/timing/time_64bit.v +++ b/usrp2/timing/time_64bit.v @@ -6,7 +6,9 @@ module time_64bit (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, input pps, - output [63:0] vita_time, output pps_int, + output [63:0] vita_time, + output reg [63:0] vita_time_pps, + output pps_int, input exp_time_in, output exp_time_out, output [31:0] debug ); @@ -74,6 +76,10 @@ module time_64bit pps_del <= {pps_del[0],pps_reg}; assign pps_edge = pps_del[0] & ~pps_del[1]; + + always @(posedge clk) + if(pps_edge) + vita_time_pps <= vita_time; always @(posedge clk) if(rst) |