Merge branch 'udp' into u1e

3 files changed, 121 insertions, 8 deletions

diff --git a/usrp2/timing/simple_timer.v b/usrp2/timing/simple_timer.v
new file mode 100644
index 000000000..17c7f1c36
--- /dev/null
+++ b/usrp2/timing/simple_timer.v
@@ -0,0 +1,60 @@
+
+
+module simple_timer
+  #(parameter BASE=0)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    output reg onetime_int, output reg periodic_int);
+
+   reg [31:0]  onetime_ctr;
+   always @(posedge clk)
+     if(reset)
+       begin
+	  onetime_int 	  <= 0;
+	  onetime_ctr 	  <= 0;
+       end
+     else
+       if(set_stb & (set_addr == BASE))
+	 begin
+	    onetime_int   <= 0;
+	    onetime_ctr   <= set_data;
+	 end
+       else 
+	 begin
+	    if(onetime_ctr == 1)
+	      onetime_int <= 1;
+	    if(onetime_ctr != 0)
+	      onetime_ctr <= onetime_ctr - 1;
+	    else
+	      onetime_int <= 0;
+	 end // else: !if(set_stb & (set_addr == BASE))
+   
+   reg [31:0]  periodic_ctr, period;
+   always @(posedge clk)
+     if(reset)
+       begin
+	  periodic_int 	     <= 0;
+	  periodic_ctr 	     <= 0;
+	  period 	     <= 0;
+       end
+     else
+       if(set_stb & (set_addr == (BASE+1)))
+	 begin
+	    periodic_int     <= 0;
+	    periodic_ctr     <= set_data;
+	    period 	     <= set_data;
+	 end
+       else 
+	 if(periodic_ctr == 1)
+	   begin
+	      periodic_int   <= 1;
+	      periodic_ctr   <= period;
+	   end
+	 else
+	   if(periodic_ctr != 0)
+	     begin
+		periodic_int <= 0;
+		periodic_ctr <= periodic_ctr - 1;
+	     end
+   
+endmodule // simple_timer
diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index c0a846e74..8ccde3f54 100644
--- a/usrp2/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
@@ -6,19 +6,28 @@ module time_64bit
     (input clk, input rst,
      input set_stb, input [7:0] set_addr, input [31:0] set_data,  
      input pps,
-     output [63:0] vita_time
+     output [63:0] vita_time, output pps_int
      );
 
-   localparam 	   NEXT_TICKS = 0;
-   localparam 	   NEXT_SECS = 1;   
+   localparam 	   NEXT_SECS = 0;   
+   localparam 	   NEXT_TICKS = 1;
+   localparam      PPS_POLSRC = 2;
+   localparam      PPS_IMM = 3;
+   
    localparam 	   ROLLOVER = TICKS_PER_SEC - 1;	   
    
+   reg [31:0] 	   seconds;
+   reg [31:0] 	   ticks;
+   wire 	   end_of_second;
    assign 	   vita_time = {seconds,ticks};
    
    wire [31:0] 	   next_ticks_preset;
    wire [31:0] 	   next_seconds_preset;
    wire 	   set_on_pps_trig;
    reg 		   set_on_next_pps;
+   wire 	   pps_polarity;
+   wire            set_imm;
+   wire 	   pps_source;
    
    setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -27,18 +36,37 @@ module time_64bit
    setting_reg #(.my_addr(BASE+NEXT_SECS)) sr_next_secs
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
+
+   setting_reg #(.my_addr(BASE+PPS_POLSRC)) sr_pps_polsrc
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({pps_source,pps_polarity}),.changed());
+
+   setting_reg #(.my_addr(BASE+PPS_IMM)) sr_pps_imm
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(set_imm),.changed());
+
+   reg [1:0] 	   pps_del;
+   reg 		   pps_reg_p, pps_reg_n, pps_reg;
+   wire 	   pps_edge;
    
-   reg [31:0] 	   seconds;
-   reg [31:0] 	   ticks;
+   always @(posedge clk)  pps_reg_p <= pps;   
+   always @(negedge clk)  pps_reg_n <= pps;
+   always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n;
    
-   wire 	   end_of_second;
+   always @(posedge clk)
+     if(rst)
+       pps_del <= 2'b00;
+     else
+       pps_del <= {pps_del[0],pps_reg};
+
+   assign pps_edge = pps_del[0] & ~pps_del[1];
    
    always @(posedge clk)
      if(rst)
        set_on_next_pps <= 0;
      else if(set_on_pps_trig)
        set_on_next_pps <= 1;
-     else if(pps)
+     else if(set_imm | pps_edge)
        set_on_next_pps <= 0;
    
    always @(posedge clk)
@@ -47,7 +75,7 @@ module time_64bit
 	  seconds <= 32'd0;
 	  ticks <= 32'd0;
        end
-     else if(pps & set_on_next_pps)
+     else if((set_imm | pps_edge) & set_on_next_pps)
        begin
 	  seconds <= next_seconds_preset;
 	  ticks <= next_ticks_preset;
@@ -59,5 +87,7 @@ module time_64bit
        end
      else
        ticks <= ticks + 1;
+
+   assign pps_int = pps_edge;
    
 endmodule // time_64bit
diff --git a/usrp2/timing/time_compare.v b/usrp2/timing/time_compare.v
new file mode 100644
index 000000000..a21c9f8e0
--- /dev/null
+++ b/usrp2/timing/time_compare.v
@@ -0,0 +1,23 @@
+
+// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second
+
+module time_compare
+  (input [63:0] time_now,
+   input [63:0] trigger_time,
+   output now,
+   output early,
+   output late, 
+   output too_early);
+   
+   wire    sec_match   = (time_now[63:32] == trigger_time[63:32]);
+   wire    sec_late    = (time_now[63:32] > trigger_time[63:32]);
+
+   wire    tick_match  = (time_now[31:0] == trigger_time[31:0]);
+   wire    tick_late   = (time_now[31:0] > trigger_time[31:0]);
+   
+   assign now 	       = sec_match & tick_match;
+   assign late 	       = sec_late | (sec_match & tick_late);
+   assign early        = ~now & ~late;
+   assign too_early    = (trigger_time[63:32] > (time_now[63:32] + 4));  // Don't wait too long
+   
+endmodule // time_compare