simplify time comparison to speed up logic and meet fpga timing

1 files changed, 25 insertions, 1 deletions

diff --git a/usrp2/timing/time_compare.v b/usrp2/timing/time_compare.v
index a21c9f8e0..cb2b6d860 100644
--- a/usrp2/timing/time_compare.v
+++ b/usrp2/timing/time_compare.v
@@ -14,10 +14,34 @@ module time_compare
 
    wire    tick_match  = (time_now[31:0] == trigger_time[31:0]);
    wire    tick_late   = (time_now[31:0] > trigger_time[31:0]);
-   
+/*   
    assign now 	       = sec_match & tick_match;
    assign late 	       = sec_late | (sec_match & tick_late);
    assign early        = ~now & ~late;
+*/
+
+   /*
+   assign now = (time_now == trigger_time);
+   assign late = (time_now > trigger_time);
+   assign early = (time_now < trigger_time);
+   */
+
+   // Compare fewer bits instead of 64 to speed up logic
+   // Unused bits are not significant
+   //     Top bit of seconds would put us in year 2038, long after
+   //        the warranty has run out :)
+   //     Top 5 bits of ticks are always zero for clocks less than 134MHz
+   //     "late" can drop bottom few bits of ticks, and just delay signaling
+   //        of late.  
+   //     "now" cannot drop those bits, it needs to be exact.
+   
+   wire [57:0] short_now = {time_now[62:32],time_now[26:0]};
+   wire [57:0] short_trig = {trigger_time[62:32],trigger_time[26:0]};
+
+   assign now = (short_now == short_trig);
+   assign late = (short_now[57:5] > short_trig[57:5]);
+   assign early = (short_now < short_trig);
+   
    assign too_early    = (trigger_time[63:32] > (time_now[63:32] + 4));  // Don't wait too long
    
 endmodule // time_compare