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authorMatt Ettus <matt@ettus.com>2011-07-21 15:24:56 -0700
committerMatt Ettus <matt@ettus.com>2011-07-21 15:24:56 -0700
commitf281c2230a25c84351c0adc1bbae535edd5d260e (patch)
tree309b942f347d94e32f5a077043ae10f4734f4244 /usrp2/timing
parent0f50e9de3a2bb65b170aa5d1e450ce7996ce0ec3 (diff)
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u2/u2p: further qualify the serdes link light
Diffstat (limited to 'usrp2/timing')
-rw-r--r--usrp2/timing/time_64bit.v7
1 files changed, 7 insertions, 0 deletions
diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index d32f4220b..8c9090a35 100644
--- a/usrp2/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
@@ -27,6 +27,7 @@ module time_64bit
output reg [63:0] vita_time_pps,
output pps_int,
input exp_time_in, output exp_time_out,
+ output reg good_sync,
output [31:0] debug
);
@@ -164,5 +165,11 @@ module time_64bit
assign debug = { { 24'b0} ,
{ 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} };
+
+ always @(posedge clk)
+ if(rst)
+ good_sync <= 0;
+ else if(sync_rcvd)
+ good_sync <= 1;
endmodule // time_64bit