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| author | Ian Buckley <ianb@server2.(none)> | 2010-07-31 00:15:16 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 11:47:57 -0800 |
| commit | b48b0f171b9e24c161efc6d2b1d2b1a1dbb0324d (patch) | |
| tree | 38b9b9c94b83bb22e49a359c096b8ef6621dbd50 /usrp2/timing/time_receiver.v | |
| parent | fb73ea172526319803756b985dd3c104881304b1 (diff) | |
| download | uhd-b48b0f171b9e24c161efc6d2b1d2b1a1dbb0324d.tar.gz uhd-b48b0f171b9e24c161efc6d2b1d2b1a1dbb0324d.tar.bz2 uhd-b48b0f171b9e24c161efc6d2b1d2b1a1dbb0324d.zip | |
External FIFO tested in simulation and on USRP2 from decimation 64->8 with current head UHD code.
Apparently operation is "flawless" but more regression and corner case regression could and should be done.
Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good
practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
Diffstat (limited to 'usrp2/timing/time_receiver.v')
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