summaryrefslogtreecommitdiffstats
path: root/usrp2/timing/time_64bit.v
diff options
context:
space:
mode:
authorMatt Ettus <matt@ettus.com>2010-01-25 13:24:53 -0800
committerMatt Ettus <matt@ettus.com>2010-01-25 13:24:53 -0800
commit058780d92f776bcba0a384b5e4c4aa948d64c6f4 (patch)
tree265ec9cbeb67bdbc0529b22209eb37f57008dc25 /usrp2/timing/time_64bit.v
parenta8ceedc34bb66c870964e4430c098a2cdaf9d429 (diff)
parent8d19387a8642caf74179bdcb7eddf1936f473e53 (diff)
downloaduhd-058780d92f776bcba0a384b5e4c4aa948d64c6f4.tar.gz
uhd-058780d92f776bcba0a384b5e4c4aa948d64c6f4.tar.bz2
uhd-058780d92f776bcba0a384b5e4c4aa948d64c6f4.zip
Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp
Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
Diffstat (limited to 'usrp2/timing/time_64bit.v')
-rw-r--r--usrp2/timing/time_64bit.v17
1 files changed, 12 insertions, 5 deletions
diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index 84f79645c..8ccde3f54 100644
--- a/usrp2/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
@@ -11,7 +11,8 @@ module time_64bit
localparam NEXT_SECS = 0;
localparam NEXT_TICKS = 1;
- localparam PPS_POL = 2;
+ localparam PPS_POLSRC = 2;
+ localparam PPS_IMM = 3;
localparam ROLLOVER = TICKS_PER_SEC - 1;
@@ -25,6 +26,8 @@ module time_64bit
wire set_on_pps_trig;
reg set_on_next_pps;
wire pps_polarity;
+ wire set_imm;
+ wire pps_source;
setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -34,9 +37,13 @@ module time_64bit
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
- setting_reg #(.my_addr(BASE+PPS_POL)) sr_pps_pol
+ setting_reg #(.my_addr(BASE+PPS_POLSRC)) sr_pps_polsrc
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(pps_polarity),.changed());
+ .in(set_data),.out({pps_source,pps_polarity}),.changed());
+
+ setting_reg #(.my_addr(BASE+PPS_IMM)) sr_pps_imm
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(set_imm),.changed());
reg [1:0] pps_del;
reg pps_reg_p, pps_reg_n, pps_reg;
@@ -59,7 +66,7 @@ module time_64bit
set_on_next_pps <= 0;
else if(set_on_pps_trig)
set_on_next_pps <= 1;
- else if(pps_edge)
+ else if(set_imm | pps_edge)
set_on_next_pps <= 0;
always @(posedge clk)
@@ -68,7 +75,7 @@ module time_64bit
seconds <= 32'd0;
ticks <= 32'd0;
end
- else if(pps_edge & set_on_next_pps)
+ else if((set_imm | pps_edge) & set_on_next_pps)
begin
seconds <= next_seconds_preset;
ticks <= next_ticks_preset;