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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
| commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
| tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /usrp2/testbench | |
| parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
| download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip | |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'usrp2/testbench')
| -rw-r--r-- | usrp2/testbench/.gitignore | 5 | ||||
| -rw-r--r-- | usrp2/testbench/Makefile | 10 | ||||
| -rw-r--r-- | usrp2/testbench/README | 5 | ||||
| -rw-r--r-- | usrp2/testbench/cmdfile | 27 |
4 files changed, 47 insertions, 0 deletions
diff --git a/usrp2/testbench/.gitignore b/usrp2/testbench/.gitignore new file mode 100644 index 000000000..eedcf9652 --- /dev/null +++ b/usrp2/testbench/.gitignore @@ -0,0 +1,5 @@ +/single_u2_sim +/dual_u2_sim +/*.lxt +/*.vcd +/*.sav diff --git a/usrp2/testbench/Makefile b/usrp2/testbench/Makefile new file mode 100644 index 000000000..6032a0123 --- /dev/null +++ b/usrp2/testbench/Makefile @@ -0,0 +1,10 @@ +all: single dual + +single: + iverilog -Wimplicit -Wportbind -c cmdfile ../top/single_u2_sim/single_u2_sim.v -o single_u2_sim + +dual: + iverilog -Wimplicit -Wportbind -c cmdfile ../top/dual_u2_sim/dual_u2_sim.v -o dual_u2_sim + +clean: + rm -f single_u2_sim dual_u2_sim *.vcd *.lxt diff --git a/usrp2/testbench/README b/usrp2/testbench/README new file mode 100644 index 000000000..14bbb68bb --- /dev/null +++ b/usrp2/testbench/README @@ -0,0 +1,5 @@ +The path to happiness: + +make clean +make +./u2_sim +rom=../../firmware/eth_test.rom -lxt2 diff --git a/usrp2/testbench/cmdfile b/usrp2/testbench/cmdfile new file mode 100644 index 000000000..8083eb92a --- /dev/null +++ b/usrp2/testbench/cmdfile @@ -0,0 +1,27 @@ + +# My stuff +-y . +-y ../top/u2_core +-y ../control_lib +-y ../control_lib/newfifo +-y ../serdes +-y ../sdr_lib +-y ../timing +-y ../coregen +-y ../extram +-y ../simple_gemac +-y ../simple_gemac/miim + +# Models +-y ../models +-y ../models/CY7C1356C + +# Open Cores +-y ../opencores/8b10b +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog +-y ../opencores/aemb/rtl/verilog +-y ../opencores/simple_pic/rtl + |