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authorJosh Blum <josh@joshknows.com>2010-01-22 16:00:45 -0800
committerJosh Blum <josh@joshknows.com>2010-01-22 16:00:45 -0800
commit8b377a9d6d0ad281474a8dbff49ea3b093178b28 (patch)
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+# My stuff
+-y .
+-y ../top/u2_core
+-y ../control_lib
+-y ../control_lib/newfifo
+-y ../serdes
+-y ../sdr_lib
+-y ../timing
+-y ../coregen
+-y ../extram
+-y ../simple_gemac
+-y ../simple_gemac/miim
+
+# Models
+-y ../models
+-y ../models/CY7C1356C
+
+# Open Cores
+-y ../opencores/8b10b
+-y ../opencores/spi/rtl/verilog
++incdir+../opencores/spi/rtl/verilog
+-y ../opencores/i2c/rtl/verilog
++incdir+../opencores/i2c/rtl/verilog
+-y ../opencores/aemb/rtl/verilog
+-y ../opencores/simple_pic/rtl
+