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authorJosh Blum <josh@joshknows.com>2010-01-22 11:56:55 -0800
committerJosh Blum <josh@joshknows.com>2010-01-22 11:56:55 -0800
commit7bf8a6df381a667134b55701993c6770d32bc76b (patch)
tree4a298fb5450f7277b5aaf5210740ae18f818c9aa /usrp2/testbench/Makefile
parent8f2c33eab9396185df259639082b7d1618585973 (diff)
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Moved usrp2 fpga files into usrp2 subdir.
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diff --git a/usrp2/testbench/Makefile b/usrp2/testbench/Makefile
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+all: single dual
+
+single:
+ iverilog -Wimplicit -Wportbind -c cmdfile ../top/single_u2_sim/single_u2_sim.v -o single_u2_sim
+
+dual:
+ iverilog -Wimplicit -Wportbind -c cmdfile ../top/dual_u2_sim/dual_u2_sim.v -o dual_u2_sim
+
+clean:
+ rm -f single_u2_sim dual_u2_sim *.vcd *.lxt