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| author | Matt Ettus <matt@ettus.com> | 2011-03-03 17:00:31 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-03 17:00:31 -0800 |
| commit | d5c8cd25172c9c6f6de85e55813fafd0cb35a776 (patch) | |
| tree | 26a63716eb982e08e7017a73dccf3aee9d0b92ae /usrp2/simple_gemac | |
| parent | b958e4b6b0d60fb9c32cee2e5aab84899029c8f9 (diff) | |
| download | uhd-d5c8cd25172c9c6f6de85e55813fafd0cb35a776.tar.gz uhd-d5c8cd25172c9c6f6de85e55813fafd0cb35a776.tar.bz2 uhd-d5c8cd25172c9c6f6de85e55813fafd0cb35a776.zip | |
u2/u2p: remove duplicated short fifo
Diffstat (limited to 'usrp2/simple_gemac')
| -rw-r--r-- | usrp2/simple_gemac/simple_gemac_wrapper.v | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v index d64ff638a..b783729d5 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -105,8 +105,7 @@ module simple_gemac_wrapper // TX FIFO Chain wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; - wire [7:0] tx_ll_data, tx_ll_data2; + wire [7:0] tx_ll_data; wire [35:0] tx_f36_data_int1; wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; @@ -118,16 +117,9 @@ module simple_gemac_wrapper fifo36_to_ll8 fifo36_to_ll8 (.clk(tx_clk), .reset(tx_reset), .clear(clear), .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), - .ll_data(tx_ll_data2), .ll_sof(tx_ll_sof2), .ll_eof(tx_ll_eof2), - .ll_src_rdy(tx_ll_src_rdy2), .ll_dst_rdy(tx_ll_dst_rdy2)); + .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), + .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy)); - ll8_shortfifo tx_sfifo - (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), - .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2), - .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), - .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); - ll8_to_txmac ll8_to_txmac (.clk(tx_clk), .reset(tx_reset), .clear(clear), .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), @@ -143,8 +135,7 @@ module simple_gemac_wrapper wire [31:0] debug_tx, debug_rx; assign debug_tx = { { tx_ll_data }, - { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, - tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, + { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 4'b0 }, { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, { tx_data} }; assign debug_rx = { { rx_ll_data }, |