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| author | Matt Ettus <matt@ettus.com> | 2011-03-15 13:44:37 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-16 12:26:38 -0700 |
| commit | 2b4f49ea92999ab234204a7fad79e4cf7148a977 (patch) | |
| tree | 63b699f97df062b6fb48406bdc2964ec3ecf494e /usrp2/simple_gemac | |
| parent | 61e351ac3db6afa061a828f4df3e6cb1a37d0380 (diff) | |
| download | uhd-2b4f49ea92999ab234204a7fad79e4cf7148a977.tar.gz uhd-2b4f49ea92999ab234204a7fad79e4cf7148a977.tar.bz2 uhd-2b4f49ea92999ab234204a7fad79e4cf7148a977.zip | |
eth: add padding on incoming packets, remove on outgoing packets
Diffstat (limited to 'usrp2/simple_gemac')
| -rw-r--r-- | usrp2/simple_gemac/simple_gemac_wrapper.v | 13 | ||||
| -rw-r--r-- | usrp2/simple_gemac/simple_gemac_wrapper19.v | 1 |
2 files changed, 9 insertions, 5 deletions
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v index b783729d5..08a3c9894 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -106,17 +106,22 @@ module simple_gemac_wrapper // TX FIFO Chain wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; wire [7:0] tx_ll_data; - wire [35:0] tx_f36_data_int1; - wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; + wire [35:0] tx_f36_data_int1, tx_f36_data_int2; + wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_src_rdy_int2, tx_f36_dst_rdy_int2; fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), .rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset)); - + + ethtx_realign ethtx_realign + (.clk(rx_clk), .reset(tx_reset), .clear(clear), + .datain(tx_f36_data_int1), .src_rdy_i(tx_f36_src_rdy_int1), .dst_rdy_o(tx_f36_dst_rdy_int1), + .dataout(tx_f36_data_int2), .src_rdy_o(tx_f36_src_rdy_int2), .dst_rdy_i(tx_f36_dst_rdy_int2) ); + fifo36_to_ll8 fifo36_to_ll8 (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), + .f36_data(tx_f36_data_int2), .f36_src_rdy_i(tx_f36_src_rdy_int2), .f36_dst_rdy_o(tx_f36_dst_rdy_int2), .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy)); diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.v b/usrp2/simple_gemac/simple_gemac_wrapper19.v index c155b7d41..2ac8b9be1 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper19.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper19.v @@ -90,7 +90,6 @@ module simple_gemac_wrapper19 .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) ); - //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo (.wclk(rx_clk), .datain(rx_f19_data_int2), .src_rdy_i(rx_f19_src_rdy_int2), .dst_rdy_o(rx_f19_dst_rdy_int2), .space(rx_fifo_space), |