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| author | Matt Ettus <matt@ettus.com> | 2011-03-15 15:04:22 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-16 12:26:38 -0700 |
| commit | 5ebb3729699441e3a1f0d661449c05da8d240cd2 (patch) | |
| tree | 59c5d6204b1f5c6ed92c3b34422876b290369b2d /usrp2/simple_gemac | |
| parent | a3caf028dcc498216ee8007382a83b83554a3cf9 (diff) | |
| download | uhd-5ebb3729699441e3a1f0d661449c05da8d240cd2.tar.gz uhd-5ebb3729699441e3a1f0d661449c05da8d240cd2.tar.bz2 uhd-5ebb3729699441e3a1f0d661449c05da8d240cd2.zip | |
eth: the danger of cut and paste
Diffstat (limited to 'usrp2/simple_gemac')
| -rw-r--r-- | usrp2/simple_gemac/ethrx_realign.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/simple_gemac/ethrx_realign.v b/usrp2/simple_gemac/ethrx_realign.v index e0987e408..0a369c914 100644 --- a/usrp2/simple_gemac/ethrx_realign.v +++ b/usrp2/simple_gemac/ethrx_realign.v @@ -1,7 +1,7 @@ // NOTE: Will not work with single-line frames -module ethtx_realign +module ethrx_realign (input clk, input reset, input clear, input [35:0] datain, input src_rdy_i, output dst_rdy_o, output [35:0] dataout, output src_rdy_o, input dst_rdy_i); @@ -69,4 +69,4 @@ module ethtx_realign assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]}; assign src_rdy_o = (state == RE_DONE) | src_rdy_i; assign dst_rdy_o = dst_rdy_i & ((state == RE_IDLE)|(state == RE_HELD)); -endmodule // ethtx_realign +endmodule // ethrx_realign |