dsp rework: pass vita clears into dsp modules, unified fifo clears

4 files changed, 10 insertions, 10 deletions

diff --git a/usrp2/sdr_lib/ddc_chain.v b/usrp2/sdr_lib/ddc_chain.v
index 3dee978a5..800bb5b13 100644
--- a/usrp2/sdr_lib/ddc_chain.v
+++ b/usrp2/sdr_lib/ddc_chain.v
@@ -19,7 +19,7 @@
 
 module ddc_chain
   #(parameter BASE = 0, parameter DSPNO = 0)
-  (input clk, input rst,
+  (input clk, input rst, input clr,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
 
@@ -166,7 +166,7 @@ module ddc_chain
      (.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(ddc_chain_out[15:0]), .strobe_out());
 
    dsp_rx_glue #(.DSPNO(DSPNO)) custom(
-    .clock(clk), .reset(rst), .enable(run),
+    .clock(clk), .reset(rst), .clear(clr), .enable(run),
     .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
     .frontend_i(rx_fe_i_mux), .frontend_q(rx_fe_q_mux),
     .ddc_in_i(to_cordic_i), .ddc_in_q(to_cordic_q),
diff --git a/usrp2/sdr_lib/dsp_rx_glue.v b/usrp2/sdr_lib/dsp_rx_glue.v
index 2c7c188e0..e2a1d52b1 100644
--- a/usrp2/sdr_lib/dsp_rx_glue.v
+++ b/usrp2/sdr_lib/dsp_rx_glue.v
@@ -28,7 +28,7 @@ module dsp_rx_glue
 )
 (
     //control signals
-    input clock, input reset, input enable,
+    input clock, input reset, input clear, input enable,
 
     //user settings bus, controlled through user setting regs API
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -63,7 +63,7 @@ module dsp_rx_glue
             `else
             RX_DSP0_MODULE rx_dsp0_custom
             (
-                .clock(clock), .reset(reset), .enable(enable),
+                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                 .frontend_i(frontend_i), .frontend_q(frontend_q),
                 .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
@@ -81,7 +81,7 @@ module dsp_rx_glue
             `else
             RX_DSP1_MODULE rx_dsp1_custom
             (
-                .clock(clock), .reset(reset), .enable(enable),
+                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                 .frontend_i(frontend_i), .frontend_q(frontend_q),
                 .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
diff --git a/usrp2/sdr_lib/dsp_tx_glue.v b/usrp2/sdr_lib/dsp_tx_glue.v
index 8eccd2bfc..9af13c6c1 100644
--- a/usrp2/sdr_lib/dsp_tx_glue.v
+++ b/usrp2/sdr_lib/dsp_tx_glue.v
@@ -28,7 +28,7 @@ module dsp_tx_glue
 )
 (
     //control signals
-    input clock, input reset, input enable,
+    input clock, input reset, input clear, input enable,
 
     //user settings bus, controlled through user setting regs API
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -63,7 +63,7 @@ module dsp_tx_glue
             `else
             TX_DSP0_MODULE tx_dsp0_custom
             (
-                .clock(clock), .reset(reset), .enable(enable),
+                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                 .frontend_i(frontend_i), .frontend_q(frontend_q),
                 .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
@@ -81,7 +81,7 @@ module dsp_tx_glue
             `else
             TX_DSP1_MODULE tx_dsp1_custom
             (
-                .clock(clock), .reset(reset), .enable(enable),
+                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                 .frontend_i(frontend_i), .frontend_q(frontend_q),
                 .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
diff --git a/usrp2/sdr_lib/duc_chain.v b/usrp2/sdr_lib/duc_chain.v
index d3b2b394f..7a72903a6 100644
--- a/usrp2/sdr_lib/duc_chain.v
+++ b/usrp2/sdr_lib/duc_chain.v
@@ -19,7 +19,7 @@
 
 module duc_chain
   #(parameter BASE = 0, parameter DSPNO = 0)
-  (input clk, input rst,
+  (input clk, input rst, input clr,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
 
@@ -148,7 +148,7 @@ module duc_chain
       );
 
    dsp_tx_glue #(.DSPNO(DSPNO)) dsp_tx_glue(
-    .clock(clk), .reset(rst), .enable(run),
+    .clock(clk), .reset(rst), .clear(clr), .enable(run),
     .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
     .frontend_i(tx_fe_i), .frontend_q(tx_fe_q),
     .duc_out_i(prod_i[33:10]), .duc_out_q(prod_q[33:10]),