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| author | Matt Ettus <matt@ettus.com> | 2010-07-16 16:16:45 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-07-16 16:16:45 -0700 |
| commit | ed0679e33f7405e33816b7d6a4dce80a54a5cf40 (patch) | |
| tree | dfe613451b4b02676680966b6287a82bdfa941df /usrp2/sdr_lib | |
| parent | cc1a35023361784adb05f1159c3ba8f5ececc6a5 (diff) | |
| download | uhd-ed0679e33f7405e33816b7d6a4dce80a54a5cf40.tar.gz uhd-ed0679e33f7405e33816b7d6a4dce80a54a5cf40.tar.bz2 uhd-ed0679e33f7405e33816b7d6a4dce80a54a5cf40.zip | |
remove warnings
Diffstat (limited to 'usrp2/sdr_lib')
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_tx.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v index 22d3d44a3..79d92c9b3 100644 --- a/usrp2/sdr_lib/dsp_core_tx.v +++ b/usrp2/sdr_lib/dsp_core_tx.v @@ -29,11 +29,11 @@ module dsp_core_tx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({scale_i,scale_q}),.changed()); - setting_reg #(.my_addr(BASE+2)) sr_2 + setting_reg #(.my_addr(BASE+2), .width(10)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed()); - setting_reg #(.my_addr(BASE+4)) sr_4 + setting_reg #(.my_addr(BASE+4), .width(8)) sr_4 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({dacmux_b,dacmux_a}),.changed()); |