dsp rework: integrated custom dsp module shells

2 files changed, 34 insertions, 15 deletions

diff --git a/usrp2/sdr_lib/ddc_chain.v b/usrp2/sdr_lib/ddc_chain.v
index 02544a0fe..86ff2001b 100644
--- a/usrp2/sdr_lib/ddc_chain.v
+++ b/usrp2/sdr_lib/ddc_chain.v
@@ -18,9 +18,10 @@
 //! The USRP digital down-conversion chain
 
 module ddc_chain
-  #(parameter BASE = 0)
+  #(parameter BASE = 0, parameter DSPNO = 0)
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+   input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
 
    // From RX frontend
    input [23:0] rx_fe_i,
@@ -91,10 +92,12 @@ module ddc_chain
      else
        phase <= phase + phase_inc;
 
+   wire [23:0] to_cordic_i, to_cordic_q;
+
    // CORDIC  24-bit I/O
    cordic_z24 #(.bitwidth(25))
      cordic(.clock(clk), .reset(rst), .enable(run),
-	    .xi({rx_fe_i_mux[23],rx_fe_i_mux}),. yi({rx_fe_q_mux[23],rx_fe_q_mux}), .zi(phase[31:8]),
+	    .xi({to_cordic_i[23],to_cordic_i}),. yi({to_cordic_q[23],to_cordic_q}), .zi(phase[31:8]),
 	    .xo(i_cordic),.yo(q_cordic),.zo() );
 
    clip_reg #(.bits_in(25), .bits_out(24)) clip_i
@@ -136,12 +139,22 @@ module ddc_chain
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
    // Round final answer to 16 bits
+   wire [31:0] ddc_chain_out;
+   wire ddc_chain_stb;
    round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i
-     (.clk(clk),.reset(rst), .in(i_hb2),.strobe_in(strobe_hb2), .out(sample[31:16]), .strobe_out(strobe));
+     (.clk(clk),.reset(rst), .in(i_hb2),.strobe_in(strobe_hb2), .out(ddc_chain_out[31:16]), .strobe_out(ddc_chain_stb));
 
    round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q
-     (.clk(clk),.reset(rst), .in(q_hb2),.strobe_in(strobe_hb2), .out(sample[15:0]), .strobe_out());
-   
+     (.clk(clk),.reset(rst), .in(q_hb2),.strobe_in(strobe_hb2), .out(ddc_chain_out[15:0]), .strobe_out());
+
+   custom_dsp_rx #(.DSPNO(DSPNO)) custom(
+    .clock(clk), .reset(rst), .enable(run),
+    .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
+    .frontend_i(rx_fe_i_mux), .frontend_q(rx_fe_q_mux),
+    .ddc_in_i(to_cordic_i), .ddc_in_q(to_cordic_q),
+    .ddc_out_sample(ddc_chain_out), .ddc_out_strobe(ddc_chain_stb),
+    .bb_sample(sample), .bb_strobe(strobe));
+
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2};
    
 endmodule // ddc_chain
diff --git a/usrp2/sdr_lib/duc_chain.v b/usrp2/sdr_lib/duc_chain.v
index 0d3ca258f..66d15d0ad 100644
--- a/usrp2/sdr_lib/duc_chain.v
+++ b/usrp2/sdr_lib/duc_chain.v
@@ -18,15 +18,16 @@
 //! The USRP digital up-conversion chain
 
 module duc_chain
-  #(parameter BASE = 0)
+  #(parameter BASE = 0, parameter DSPNO = 0)
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+   input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
 
-   // From TX frontend
+   // To TX frontend
    output [23:0] tx_fe_i,
    output [23:0] tx_fe_q,
 
-   // To TX control
+   // From TX control
    input [31:0] sample,
    input run,
    output strobe,
@@ -85,8 +86,8 @@ module duc_chain
    wire        signed [17:0] da, db;
    wire        signed [35:0] prod_i, prod_q;
 
-   wire [17:0] bb_i = {sample[31:16],2'b0};
-   wire [17:0] bb_q = {sample[15:0],2'b0};
+   wire [15:0] bb_i;
+   wire [15:0] bb_q;
    wire [17:0] i_interp, q_interp;
 
    wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
@@ -96,9 +97,9 @@ module duc_chain
    //   but the default case inside hb_interp handles this
    
    hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_i
-     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_i),.stb_out(strobe_hb2),.data_out(hb1_i));
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_i, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_i));
    hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_q
-     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_q),.stb_out(strobe_hb2),.data_out(hb1_q));
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in({bb_q, 2'b0}),.stb_out(strobe_hb2),.data_out(hb1_q));
    
    small_hb_int #(.WIDTH(18)) small_hb_interp_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
@@ -148,9 +149,14 @@ module duc_chain
       .R(rst)     // Synchronous reset input
       );
 
-   assign tx_fe_i = prod_i[28:5];
-   assign tx_fe_q = prod_q[28:5];
-   
+   custom_dsp_tx #(.DSPNO(DSPNO)) custom(
+    .clock(clk), .reset(rst), .enable(run),
+    .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
+    .frontend_i(tx_fe_i), .frontend_q(tx_fe_q),
+    .duc_out_i(prod_i[28:5]), .duc_out_q(prod_q[28:5]),
+    .duc_in_sample({bb_i, bb_q}), .duc_in_strobe(strobe_hb1),
+    .bb_sample(sample), .bb_strobe(strobe));
+
    assign      debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
 
 endmodule // dsp_core