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| author | Matt Ettus <matt@ettus.com> | 2011-06-07 13:32:18 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-08 10:55:22 -0700 |
| commit | 5971f8e8ff288e3b1e688f6268ef536f0875238b (patch) | |
| tree | 98bfe52b0871bfe8b8fcc6568d7f9ccb11a97a4d /usrp2/sdr_lib | |
| parent | d7a3b89d4f7fea444602b0f8ff52029b0efa835f (diff) | |
| download | uhd-5971f8e8ff288e3b1e688f6268ef536f0875238b.tar.gz uhd-5971f8e8ff288e3b1e688f6268ef536f0875238b.tar.bz2 uhd-5971f8e8ff288e3b1e688f6268ef536f0875238b.zip | |
dsp: remove unused setting reg
Diffstat (limited to 'usrp2/sdr_lib')
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_tx.v | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v index 66dcee261..f02c63b42 100644 --- a/usrp2/sdr_lib/dsp_core_tx.v +++ b/usrp2/sdr_lib/dsp_core_tx.v @@ -49,10 +49,6 @@ module dsp_core_tx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed()); - setting_reg #(.my_addr(BASE+4), .width(8)) sr_4 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({dacmux_b,dacmux_a}),.changed()); - // Strobes are all now delayed by 1 cycle for timing reasons wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre; reg strobe_cic = 1; |