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author | Josh Blum <josh@joshknows.com> | 2011-07-08 12:14:53 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2011-07-08 12:14:53 -0700 |
commit | 4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4 (patch) | |
tree | d2e66eb4e5f7cf7f8ab033f5482a6f2477aa88b6 /usrp2/sdr_lib/round_reg.v | |
parent | dd41da159157afe417e7f3b77ba30e189eb510fe (diff) | |
parent | fbc01138d5f943b06ce1bf3f746287b9d6c7789d (diff) | |
download | uhd-4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4.tar.gz uhd-4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4.tar.bz2 uhd-4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4.zip |
Merge branch 'b100_shrink' into next
Diffstat (limited to 'usrp2/sdr_lib/round_reg.v')
-rw-r--r-- | usrp2/sdr_lib/round_reg.v | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/usrp2/sdr_lib/round_reg.v b/usrp2/sdr_lib/round_reg.v index aa0972dab..6f2e974d7 100644 --- a/usrp2/sdr_lib/round_reg.v +++ b/usrp2/sdr_lib/round_reg.v @@ -27,13 +27,18 @@ module round_reg parameter bits_out=0) (input clk, input [bits_in-1:0] in, - output reg [bits_out-1:0] out); + output reg [bits_out-1:0] out, + output reg [bits_in-bits_out:0] err); wire [bits_out-1:0] temp; - - round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp)); + wire [bits_in-bits_out:0] err_temp; + + round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp)); always @(posedge clk) out <= temp; + + always @(posedge clk) + err <= err_temp; -endmodule // round +endmodule // round_reg |