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| author | Ian Buckley <ianb@server2.ionconcepts.com> | 2010-09-30 15:54:03 -0700 |
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| committer | Ian Buckley <ianb@server2.ionconcepts.com> | 2010-09-30 15:54:03 -0700 |
| commit | 1c3dfe21f8bacbf762b440a23ce652a879288615 (patch) | |
| tree | de38fdff2848091a8c2c0ac1ab201a679c5e14d6 /usrp2/sdr_lib/input.dat | |
| parent | 7ffe28ccc6059ae3caa500e35b76718ae6ff100a (diff) | |
| download | uhd-1c3dfe21f8bacbf762b440a23ce652a879288615.tar.gz uhd-1c3dfe21f8bacbf762b440a23ce652a879288615.tar.bz2 uhd-1c3dfe21f8bacbf762b440a23ce652a879288615.zip | |
Modified phase shift of DCM1 to -64 which is intended to give more timing margin on reads from the SRAM at the expense of Writes to the SRAM.
Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer.
Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
Diffstat (limited to 'usrp2/sdr_lib/input.dat')
0 files changed, 0 insertions, 0 deletions