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authorJosh Blum <josh@joshknows.com>2013-08-28 16:21:02 -0700
committerJosh Blum <josh@joshknows.com>2013-08-28 16:21:02 -0700
commit714673c7437fcd863d2bfdb8b20689d6a6d0f577 (patch)
tree7f7956a1121159f8a3a4e1e98da53545fd664ca8 /usrp2/sdr_lib/dspengine_8to16.v
parent286f0d8d3830417cbf26ac494bb960b4ba735944 (diff)
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usrp2: sc8 format swap for vita compliance
Diffstat (limited to 'usrp2/sdr_lib/dspengine_8to16.v')
-rw-r--r--usrp2/sdr_lib/dspengine_8to16.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/sdr_lib/dspengine_8to16.v b/usrp2/sdr_lib/dspengine_8to16.v
index 85187d78d..64246ac13 100644
--- a/usrp2/sdr_lib/dspengine_8to16.v
+++ b/usrp2/sdr_lib/dspengine_8to16.v
@@ -1,5 +1,5 @@
-// Copyright 2012 Ettus Research LLC
+// Copyright 2012-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -75,13 +75,13 @@ module dspengine_8to16
wire [15:0] data_in_lenx2 = {data_in_len[14:0], 1'b0} - is_odd;
reg [7:0] i8_0, q8_0;
- wire [7:0] i8_1 = access_dat_i[31:24];
- wire [7:0] q8_1 = access_dat_i[23:16];
+ wire [7:0] i8_1 = access_dat_i[15:8];
+ wire [7:0] q8_1 = access_dat_i[7:0];
reg skip;
always @(posedge clk)
- { i8_0, q8_0 } <= access_dat_i[15:0];
+ { i8_0, q8_0 } <= access_dat_i[31:16];
always @(posedge clk)
if(reset | clear)