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author | Matt Ettus <matt@ettus.com> | 2011-10-06 22:21:59 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2011-10-26 15:57:22 -0700 |
commit | f4c61186f6a81a09a038cef500d07d4ca5e65a57 (patch) | |
tree | 47d9244d4761d50ee87067324d4ba3ea38b4a028 /usrp2/sdr_lib/clip_reg.v | |
parent | c215afef149acf35cca87d1a5053d2c48957652c (diff) | |
download | uhd-f4c61186f6a81a09a038cef500d07d4ca5e65a57.tar.gz uhd-f4c61186f6a81a09a038cef500d07d4ca5e65a57.tar.bz2 uhd-f4c61186f6a81a09a038cef500d07d4ca5e65a57.zip |
dsp_engine: new way of doing DSP operations on VITA packets. Example does 16 to 8 bit conversion
Diffstat (limited to 'usrp2/sdr_lib/clip_reg.v')
-rw-r--r-- | usrp2/sdr_lib/clip_reg.v | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/usrp2/sdr_lib/clip_reg.v b/usrp2/sdr_lib/clip_reg.v index d5e98d982..9098fd5b8 100644 --- a/usrp2/sdr_lib/clip_reg.v +++ b/usrp2/sdr_lib/clip_reg.v @@ -23,16 +23,24 @@ module clip_reg #(parameter bits_in=0, - parameter bits_out=0) + parameter bits_out=0, + parameter STROBED=1'b0) (input clk, input [bits_in-1:0] in, - output reg [bits_out-1:0] out); + output reg [bits_out-1:0] out, + input strobe_in, + output reg strobe_out); wire [bits_out-1:0] temp; clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp)); + + always @(posedge clk) + strobe_out <= strobe_in; + always @(posedge clk) - out <= temp; + if(strobe_in | ~STROBED) + out <= temp; endmodule // clip_reg |