Merge branch 'master' into u1e_newbuild

Made so Makefile changes as well to get it to build
* master:
  new make works on ise12
  produces good bin files
  first attempt at cleaning up the build system
  get rid of debug stuff to help timing
  move u2_core into u2_rev3 directory to simplify directory structure and save headaches

Conflicts:
	usrp2/fifo/fifo36_to_fifo18.v
	usrp2/top/u2_rev3/Makefile
	usrp2/top/u2_rev3/Makefile.udp
	usrp2/top/u2_rev3/u2_core_udp.v

1 files changed, 27 insertions, 0 deletions

diff --git a/usrp2/opencores/Makefile.srcs b/usrp2/opencores/Makefile.srcs
new file mode 100644
index 000000000..1ccecf337
--- /dev/null
+++ b/usrp2/opencores/Makefile.srcs
@@ -0,0 +1,27 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Open Cores Sources
+##################################################
+OPENCORES_SRCS = $(abspath $(addprefix $(BASE_DIR)/../opencores/, \
+8b10b/decode_8b10b.v \
+8b10b/encode_8b10b.v \
+aemb/rtl/verilog/aeMB_bpcu.v \
+aemb/rtl/verilog/aeMB_core_BE.v \
+aemb/rtl/verilog/aeMB_ctrl.v \
+aemb/rtl/verilog/aeMB_edk32.v \
+aemb/rtl/verilog/aeMB_ibuf.v \
+aemb/rtl/verilog/aeMB_regf.v \
+aemb/rtl/verilog/aeMB_xecu.v \
+i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+i2c/rtl/verilog/i2c_master_defines.v \
+i2c/rtl/verilog/i2c_master_top.v \
+i2c/rtl/verilog/timescale.v \
+spi/rtl/verilog/spi_clgen.v \
+spi/rtl/verilog/spi_defines.v \
+spi/rtl/verilog/spi_shift.v \
+spi/rtl/verilog/spi_top16.v \
+))