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authorIan Buckley <ianb@server2.(none)>2010-09-14 11:46:58 -0700
committerIan Buckley <ianb@server2.(none)>2010-09-14 11:46:58 -0700
commit7ffe28ccc6059ae3caa500e35b76718ae6ff100a (patch)
tree81485a26b4c31df371e32e114e89acafe57b4894 /usrp2/models/adc_model.v
parentc5295159e9f6eeb9ea72edab18ff97eb55d84692 (diff)
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Enabled phase offset adjustment on DCM_INST1 which drives the external Fast SRAM clock.
Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions.
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