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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
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| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
| commit | 8b377a9d6d0ad281474a8dbff49ea3b093178b28 (patch) | |
| tree | 8e3c7a1b60f96df6e2140666d3b7afa5166d885d /usrp2/models/MULT18X18S.v | |
| parent | e92d36dcfe02afaedec348f2d8fc4523fb4e633b (diff) | |
| download | uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.gz uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.bz2 uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.zip | |
moved into subdir
Diffstat (limited to 'usrp2/models/MULT18X18S.v')
| -rw-r--r-- | usrp2/models/MULT18X18S.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/usrp2/models/MULT18X18S.v b/usrp2/models/MULT18X18S.v new file mode 100644 index 000000000..5d39eeaa6 --- /dev/null +++ b/usrp2/models/MULT18X18S.v @@ -0,0 +1,20 @@ + +// Model of the Xilinx mult18x18s for signed 18x18 bit multiplies, +// As in the Spartan 3 series + +module MULT18X18S + (output reg signed [35:0] P, + input signed [17:0] A, + input signed [17:0] B, + input C, // Clock + input CE, // Clock Enable + input R // Synchronous Reset + ); + + always @(posedge C) + if(R) + P <= 36'sd0; + else if(CE) + P <= A * B; + +endmodule // MULT18X18S |